The present invention relates generally to integrated circuits. More particularly, the present invention relates to a digital variable-delay circuit that incorporates a voltage-mixing interpolator circuit and to methods of using same to perform on-chip testing and of calibrating same.
Integrated circuits (ICs) typically contain one or more functional logic blocks (FLB), such as a microprocessor, microcontroller, graphics processor, bus interface circuit, input/output (I/O) circuit, memory circuit, and the like. IC""s are typically assembled into packages that are physically and electrically coupled to a substrate such as a printed circuit board (PCB) or a ceramic substrate to form an xe2x80x9celectronic assemblyxe2x80x9d. The xe2x80x9celectronic assemblyxe2x80x9d can be part of an xe2x80x9celectronic systemxe2x80x9d. An xe2x80x9celectronic systemxe2x80x9d is broadly defined herein as any product comprising an xe2x80x9celectronic assemblyxe2x80x9d. Examples of electronic systems include computers (e.g., desktop, laptop, hand-held, server, etc.), wireless communications devices (e.g., cellular phones, cordless phones, pagers, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, MP3 (Motion Picture Experts Group, Audio Layer 3) players, etc.), and the like.
In the field of electronic systems there is an incessant competitive pressure among manufacturers to drive the performance of their equipment up while driving down production costs. This is particularly true regarding the testing of ICs, where each new generation of IC""s must provide increased performance while generally being smaller or more compact in size. IC""s must generally be tested before they are incorporated into an electronic assembly in order to verify that each component of each FLB on the IC functions properly and to verify that the input/output (I/O) terminals of each IC operate correctly within specified timing parameters or timing margins.
In testing IC""s, it is known to employ I/O loopback or switching state (AC) testing, as for example disclosed in Related Inventions Nos. 1 and 2 above. In I/O loopback testing, data is generated by a FLB within the IC and output through the output component of each I/O buffer. Subsequently, the data is received through the input component of each I/O buffer and conveyed to the FLB to verify that the correct data has been received. In this manner, the IC can verify that the input and output components of each I/O buffer are correctly operating.
It is known to use source synchronous data transfer on busses interconnecting FLB""s within a single IC or within an electronic assembly comprising one or more IC""s. In a source synchronous interface, a receiving I/O buffer captures data based upon a strobe clock that is provided by another FLB or IC device driving the data.
The use of digital delay circuits on IC""s to assist in centering a strobe signal with respect to a data cell is known in the art, such as for example the delay locked loop disclosed in U.S. Pat. No. 5,905,391 assigned to the assignee of the present invention.
However, in order to test whether source synchronous interfaces are operating properly, it is desirable to be able to vary the delay of a digital delay circuit in order to shift a strobe signal across a full data bit cell time in order to measure the effective input latch setup and holding timing. It is also desirable to be able to calibrate a digital delay circuit to a known delay.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a significant need in the art for a digital variable-delay circuit that can be used in loop-back testing of I/O buffers on IC""s, and for methods of using such at digital variable-delay circuits for testing I/O buffers on IC""s.